Translation Look-Aside Buffers (TLBs) include entries that specify the mapping of virtual addresses to physical addresses. The TLB is often used when a computer system needs to translate a limited number of address bits into a larger memory space. For example, a computer system that uses a 32 bit address bus may need to access a memory space larger than 232 bits.
Embedded processors may have area constraints that limit the amount of storage provided for the TLB entries. Variable page sizes can increase the flexibility in using the limited TLB entries. Variable page size TLBs are often implemented using either a Content Addressable Memory (CAM) or using a limited choice of page sizes segregated into individual memory arrays. The individual memory arrays become a scarce resource that must be carefully managed by software when a large number of page sizes are required, and the CAM implementation consumes considerable power.